1. Field of the Invention
This invention relates generally to synchronous semiconductor memory devices, and more particularly, to a method and apparatus for controlling column select lines in a synchronous memory device.
2. Description of the Related Art
A Synchronous DRAM generally operates in either a pipeline mode or a prefetch mode. In a synchronous DRAM operating in a pipeline mode, an address and a command are input from outside the chip during each cycle of the system clock, and a different column selection line, which is selected by a column address, is enabled during each cycle of the system clock. However, a disadvantage of a synchronous DRAM operating in a pipeline mode is that it may malfunction when used with a system clock having a relatively high frequency.
Synchronous DRAM can be operated in a prefetch mode in an attempt to guarantee operation of the DRAM with a high frequency system clock. In a synchronous DRAM having a prefetch structure, an address and a command are input from the outside the chip once during every two cycles of the system clock, and at least two column selection lines, which are selected by at least two column addresses, are enabled at the same time during two cycles of the system clock. Such an operation is usually referred to as a 2N rule or 2-bit prefetch.
FIG. 1 is a block diagram for explaining the function of a column selection line in a synchronous DRAM. Referring to FIG. 1, a memory cell array 11 is comprised of a plurality of memory cells for storing data transmitted through each of bit line pairs BLi and BLiB (wherein "i" is from 1 to n). A switching portion 12 connects the respective bit line pairs (BLi and BLiB) to each of input/output line pairs IOi and lOiB (wherein "i" is from 1 to n) when column selection line CSLi is enabled. Thus, during a read operation, data stored in the memory cells of the memory cell array 11 is output to the outside of the chip by sequentially passing through the bit line pair, the switching portion 12 and the input/output line pair. In a write operation, data from outside of the chip passes sequentially through the input/output pair, the switching portion 12 and the bit line pair and then is stored in the memory cell of the memory cell array 11. The switching portion 12 is comprised of NMOS transistors in which the gate of each NMOS transistor is connected to CSLi, one of either the source or drain thereof is connected to the bit line, and the remaining one of the source or drain is coupled to the input/output line. These NMOS transistors are usually referred to as column selection gates.
FIG. 2 is a block diagram showing a prior art circuit for controlling a column selection line in a synchronous DRAM.
Referring to FIG. 2, the conventional circuit for controlling a column selection line includes a column decoder 21, a column selection line controller 22, a first internal clock generator 23, a second internal clock generator 24, a selector 25, a column address counter 26, a column address buffer 27, and a column pre-decoder 28. The column selection line controller 22 is composed of a column selection line enable control signal generator 22a and a column selection line disable control signal generator 22b. In FIG. 2, "CSLi" represents a column selection line, "A1" a column address input from outside of the chip, "A2" an increased column address, "CAi" a buffered address, "DCAij" a pre-decoded address, and "CLK" an external clock input from outside of the chip. Also, "PCLK1" and "PCLK2" represent first and second internal clocks, respectively, and "PCLKS" represents an internal clock selected from PCLK1 and PCLK2. "PCSLE" is a column selection line enable control signal, and "PCSLD" is a column selection line disable control signal.
FIG. 3 is a circuit diagram showing a column decoder of the column selection line control circuit shown in FIG. 2. Referring to FIG. 3, the column decoder includes a PMOS transistors P1 and P2, and NMOS transistor N1. Transistor P1 has a source to which a power supply voltage VCC is applied and a gate to which the pre-decoded address DCAij is applied. PMOS transistor P2 has a source which is connected to the drain of PMOS transistor P1, a gate to which the column selection line enable control signal PCSLE is applied and a drain which is connected to the column selection line CSLi. NMOS transistor N1 has a drain which is connected to the column selection line CSLi, a gate to which the column selection line disable control signal PCSLD is applied and a source to which a ground voltage VSS is applied. The column decoder of FIG. 3 also includes a line latch 31 for storing a signal transmitted to the column selection line CSLi. The line latch 31 includes a first inverter 11 for inverting a signal transmitted to the column selection line CSLi and a second inverter 12 for inverting the output signal of the first inverter 11 and outputting the inverted signal to the column selection line CSLi.
FIG. 4 is a circuit diagram showing the column selection line enable control signal generator of the column selection line control circuit shown in FIG. 2. Referring to FIG. 4, the column selection line enable control signal generator, which operates as a sort of inverting-delay device, includes a first inverter 13 for inverting the internal clock PCLKS, a second inverter 14 for inverting the output of the first inverter 13, and a third inverter 15 for inverting the output signal of the second inverter 14 and outputting the column selection line enable control signal PCSLE.
FIG. 5 is a circuit diagram showing the column selection line disable control signal generator of the column selection line control circuit shown in FIG. 2. Referring to FIG. 5, the column selection line disable control signal generator, which operates as a sort of delaying device, includes a first inverter 16 for inverting the internal clock PCLKS, a second inverter 17 for inverting the output of the first inverter 16 and outputting the column selection line disable control signal PCSLD.
FIG. 6 is a timing diagram showing the operation of the column selection line control circuit shown in FIG. 2 when a synchronous DRAM operates in a pipeline mode. Referring to FIG. 6, when the synchronous DRAM operates in a pipeline mode, the first internal clock PCLK1 is selected as the internal clock PCLKS. Also, a single column selection line is enabled during each cycle of the external clock CLK. That is, each of the column selection lines CSL0, CSL1, CSL2 and CSL3 is consecutively maintained in an enabled state for one cycle.
In a write cycle in the pipeline mode, input data DIN, i.e., D0, D1, D2, and D3 are sequentially input to the chip at each rising edge of the external clock CLK, and when the respective column selection lines CSL0, CSL1, CSL2 and CSL3 are enabled, the data D0, D1, D2 and D3 are consecutively stored in memory cells corresponding to the respective column selection lines CSL0, CSL1, CSL2 and CSL3 via a predetermined route not shown in FIG. 2.
FIG. 7 is a timing diagram showing the operation of the column selection line control circuit shown in FIG. 2 when the synchronous DRAM operates in a 2-bit prefetch mode.
Referring to FIG. 7, when the synchronous DRAM operates in a 2-bit prefetch mode, the second internal clock PCLK2, which has twice the cycle time of the first internal clock PCLK1, is selected as the internal clock PCLKS. Also, two column selection lines are enabled at the same time and remain enabled during two cycles of the external clock CLK. That is, the column selection lines CSL0 and CSL1 are enabled for the initial two cycles of the external clock CLK and the column selection lines CSL2 and CSL3 are enabled for the next two cycles of the external clock CLK. Accordingly, since the operational frequency inside the chip is reduced to half the frequency of the external clock CLK, the time margin for reading data from a memory cell increases when the synchronous DRAM operates in the 2-bit prefetch mode.
During a write cycle in the 2-bit prefetch mode, as in a write cycle in the pipeline mode as shown in FIG. 6, input data DIN, i.e., D0, D1, D2 and D3, are consecutively input to the chip at each rising edge of the external clock CLK. Also, as described previously, in the 2-bit prefetch mode, both CSL0 and CSL1 are enabled at the same time for the initial two cycles of the external clock CLK, and both CSL2 and CSL3 are concurrently enabled for another next two cycles of the external clock CLK.
D0, D1, D2 and D3, Which pass through a predetermined route not shown in FIG. 2, are delayed for a predetermined time. Thus, in the case of D0 and D2, since a write action begins at the beginning portion (areas "a" and "c") of the time period during which column selection lines CSL0 and CSL2 are enabled, there is sufficient time for writing to the memory cells. However, in the case of D1 and D3, since a write action begins at the end portion (areas "b" and "d") of the time period during which column selection lines CSL1 and CSL3 are enabled, there is barely adequate time for writing to the memory cells.
Therefore, with a conventional column selection line control circuit, as the external clock, i.e., the system clock, becomes faster, the time margin for writing the memory cells in the write cycle of a 2-bit prefetch structure gradually becomes inadequate.
Accordingly, a need remains for an improved scheme for controlling column select lines in synchronous semiconductor memory device.